This invention relates to a write circuit for a semiconductor storage or memory device in which bipolar elements and MOS transistors are mixed.
The conventional write circuit for a high speed semiconductor storage device is usually of a bipolar contruction and an emitter follower type. The emitter follower type of circuit, however, requires a bias current flow because of the concern that an output terminal will be in the floating state. This leads to the increase of power consumption in a standby state. Particularly, the implementation of a large bit storage device further increases the power consumption since it is usually accompanied by the increase of the number of the write circuits. Relative to a sense circuit, in order that it will not be saturated by the output from the write circuit, there must be provided some means such as adding a bias power source in the write circuit, and controlling the relation between the power source and the saturation of the sense circuit.
In order to clarify the entire construction of the conventional semiconductor storage device, the block diagram thereof is shown in FIG. 1. In the figure, A.sub.1 is an input terminal for control signal such as an address signal, a chip select signal and a write control signal. For example, in the case of 16K memory, 14 address signal lines are provided, while in the case of 64K memory, 16 address signal lines are provided. As for the other signals, two or more lines are provided therefor in both cases. Character D.sub.1 designates an input terminal of a write signal which is written or stored in the memory cell selected by the address signal.
Numeral 1 is an input buffer circuit for inputting the signals for selecting the columns of memory cells arranged in a matrix shape, among the above mentioned control signals; 2 is a decoder for decoding the output signal from the input buffer circuit 1 to select one of the columns; 3 is a driver circuit for driving the output signal from the decoder 2 to drive the columns of large load capacitance; W.sub.k is a word line corresponding to a k-th column, 5 is a memory cell selected by the word line W.sub.k ; Cn, Ca are a data line for input/output of a read/write signal for the memory cell, respectively; 6 is an input buffer circuit for inputting the signals for selecting the rows of the memory cell matrix; 7 is a decoder for decoding the output signal from the input buffer circuit 6 to select one of the rows; e.sub.l designates a signal on the l-th row selected by the decoder 7; Y.sub.m, Y.sub.n are switches selected by the signal e.sub.l, respectively; a, b are common data lines for outputting the read/write signal for the data of the memory cell through the switches Y.sub.m, Y.sub.n, respectively; 9 is a sense circuit for detecting the data of the memory cell 5 from the signals on the common data lines a, b; 10 is an output buffer circuit 9 for outputting the output signal from the sense circuit 9 to an external circuit; D.sub.0 is an output signal; D.sub.1 is a write signal; and 8 is a write circuit for outputting the write signal into the common data lines a, b. Incidentally, the explanation about the above mentioned chip select signal, write control signal, etc. has been omitted for purposes of simplification.
FIG. 2 shows the conventional write circuit 8 of FIG. 1 which is constructed by the combination of bipolar elements and MOS transistors, and is disclosed in Japanese Patent Application Laid-Open No. 58193/81. Character d.sub.1 denotes a write signal, and WE denotes a write control signal. This construction incorporates constant current circuits CI1, CI2 to define the level of output signals WC, WC, and so implies such a write circuit as always involving power consumption.